DIGITAL LOGIC WORKED EXAMPLE
From a Full-Adder Truth Table to Karnaugh Maps and a Logic Circuit
Follow one complete digital-logic problem through all three DeepCalcs tools. We will define a one-bit full adder, generate its two-output truth table, minimize SUM and CARRY separately, and translate the results into gates.
Open the complete full-adder truth table →What does a full adder do?
A full adder adds three one-bit inputs: A, B and the carry-in C. It produces two outputs. SUM is the low bit of the result, while CARRY becomes the high bit or the carry-in for the next stage.
SUM output
SUM is 1 when an odd number of inputs are 1.
SUM = A ⊕ B ⊕ CCARRY output
CARRY is 1 when at least two inputs are 1.
CARRY = AB + AC + BCStep 1: build the two-output truth table
Three inputs create 2³ = 8 rows. Read each row as the binary sum of A, B and C. For example, 1 + 1 + 0 equals binary 10, so SUM is 0 and CARRY is 1.
| m | A | B | C | SUM | CARRY | Meaning |
|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 + 0 + 0 = 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 0 + 0 + 1 = 1 |
| 2 | 0 | 1 | 0 | 1 | 0 | 0 + 1 + 0 = 1 |
| 3 | 0 | 1 | 1 | 0 | 1 | 0 + 1 + 1 = 2 |
| 4 | 1 | 0 | 0 | 1 | 0 | 1 + 0 + 0 = 1 |
| 5 | 1 | 0 | 1 | 0 | 1 | 1 + 0 + 1 = 2 |
| 6 | 1 | 1 | 0 | 0 | 1 | 1 + 1 + 0 = 2 |
| 7 | 1 | 1 | 1 | 1 | 1 | 1 + 1 + 1 = 3 |
The SUM minterms are Σm(1,2,4,7). The CARRY minterms are Σm(3,5,6,7).
Step 2: simplify the SUM output
Place 1s at minterms 1, 2, 4 and 7. No two SUM cells are adjacent in a three-variable K-map, so ordinary SOP grouping cannot remove a literal. The canonical minimum SOP remains:
SUM = A′B′C + A′BC′ + AB′C′ + ABCRecognizing the odd-parity pattern gives the more practical XOR form:
SUM = A ⊕ B ⊕ CStep 3: simplify the CARRY output
Place 1s at minterms 3, 5, 6 and 7. Minterm 7 can overlap three two-cell groups:
- Group m3 with m7. B and C remain 1, producing BC.
- Group m5 with m7. A and C remain 1, producing AC.
- Group m6 with m7. A and B remain 1, producing AB.
CARRY = AB + AC + BCEvery group is essential because m3, m5 and m6 each appear in only one of these groups. Overlapping at m7 is therefore necessary, not redundant.
Open the CARRY K-map →Step 4: derive the gate circuit
The direct circuit uses two cascaded XOR gates for SUM. CARRY uses three two-input AND gates feeding an OR stage. A common implementation first creates the intermediate signal P = A ⊕ B, then uses it in both outputs:
P = A ⊕ BSUM = P ⊕ CCARRY = AB + PCThis factored carry form is equivalent to AB + AC + BC and can reuse P.
Whether the factored circuit is cheaper depends on the available gate library, fan-in and whether the XOR signal is already needed elsewhere.
Inspect the CARRY derivation →Common mistakes in this example
- Using a half-adder truth table and forgetting the carry-in C.
- Writing SUM as ordinary OR instead of three-input XOR.
- Trying to group diagonal SUM cells in the K-map.
- Rejecting the three CARRY groups because they overlap at m7.
- Assuming the shortest SOP is automatically the cheapest hardware implementation.
Check your understanding
Why is SUM 1 for minterms 1, 2, 4 and 7?
Those rows contain an odd number of 1 inputs. XOR returns 1 for odd parity.
Why can m7 belong to all three CARRY groups?
K-map groups may overlap. Each overlap helps cover a different minterm—m3, m5 or m6—that cannot be covered by either of the other groups.
Why does the XOR form look shorter than the minimum SOP?
The SOP cost model uses AND, OR and NOT literals. XOR is a higher-level operator that represents several SOP terms internally, so the two notations use different implementation libraries.
Continue in the calculators
Change an output, test your own groups or enter another algebraic step. Each calculator preserves the problem in a shareable URL.
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